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CYDM064B16 cydm128b16 cydm256b16 1.8v 4k/8k/16k x 16 mobl ? dual-port static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-00217 rev. *h revised march 1, 2011 1.8v 4k/8k/16k x 16 mobl ? dual-port static ram features true dual ported memory cells that allow simultaneous access of the same memory location 4, 8, or 16k 16 organization ultra low operating power ? active: icc = 15 ma (typical) at 55 ns ? standby: i sb3 = 2 a (typical) small footprint: available in a 6x6 mm 100-pin pb-free vfbga port independent 1.8v, 2.5v, and 3.0v i/os full asynchronous operation automatic power down pin select for master or slave expandable data bus to 32-bits with master or slave chip select when using more than one device on-chip arbitration logic semaphores included to permit software handshaking between ports input read registers and output drive registers int flag for port-to- port communication separate upper-byte and lower-byte control industrial temperature ranges selection guide for v cc = 1.8v parameter cydm256b16, cydm128b16, CYDM064B16 unit (-55) port i/o voltages (p1-p2) 1.8v -1.8v v maximum access time 55 ns typical operating current 15 ma typical standby current for i sb1 2 a typical standby current for i sb3 2 a selection guide for v cc = 2.5v parameter cydm256b16, cydm128b16, CYDM064B16 unit (-55) port i/o voltages (p1-p2) 2.5v-2.5v v maximum access time 55 ns typical operating current 28 ma typical standby current for i sb1 6 a typical standby current for i sb3 4 a selection guide for v cc = 3.0v parameter cydm256b16, cydm128b16, CYDM064B16 unit (-55) port i/o voltages (p1-p2) 3.0v-3.0v v maximum access time 55 ns typical operating current 42 ma typical standby current for i sb1 7 a typical standby current for i sb3 6 a [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 2 of 27 logic block diagram [1, 2] io control address decode mailboxes int l int r address decode 16k x 16 dual ported array io control interrupt arbitration semaphore a [13:0] r ce r busy r io[15:0] r lb r io[15:0] l lb l oe l busy l a[13:0] l r/w l ce l m/s ub l ub r sem l sem r input read register and output drive register ce r oe r oe r r/w r r/w r odr 0 - odr 4 ce l oe l r/w l irr 0 ,irr 1 sfen notes 1. a 0 ?a 11 for 4k devices; a 0 ?a 12 for 8k devices; a 0 ?a 13 for 16k devices. 2. busy is an output in master mode and an input in slave mode. [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 3 of 27 contents 1.8v 4k/8k/16k x 16 mobl ? dual-port static ram ....... 1 features ............................................................................. 1 selection guide for vcc = 1.8v ....................................... 1 selection guide for vcc = 2.5v ....................................... 1 selection guide for vcc = 3.0v ....................................... 1 logic block diagram ........................................................ 2 pinouts .............................................................................. 4 functional description ..................................................... 6 power supply .............................................................. 6 write operation ........................................................... 6 read operation ........................................................... 6 interrupts ..................................................................... 6 busy ............................................................................ 6 master/slave ............................................................... 6 input read register .................................................... 7 output drive register .................................................. 7 semaphore operation ............ .............. .............. ......... 7 architecture ...................................................................... 7 maximum ratings ........................................................... 10 operating range ............................................................. 10 electrical characteristics for vcc = 1.8v ..................... 10 electrical characteristics for vcc = 2.5v ..................... 11 electrical characteristics for 3.0v over the operating range ............................................. 12 capacitance .................................................................... 12 ac test loads and waveforms ..................................... 13 switching characteristics for vcc = 1.8v .................... 13 switching characteristics for vcc = 2.5v .................... 15 switching characteristics for vcc = 3.0v .................... 16 switching waveforms .................................................... 18 ordering information ..................................................... 24 ordering code defintions ...... .................................... 24 package diagram ............................................................ 25 document history page ................................................. 26 sales, solutions, and legal information ...................... 27 worldwide sales and design s upport ......... .............. 27 products .................................................................... 27 psoc solutions ......................................................... 27 [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 4 of 27 pinouts figure 1. ball diagram - 100-ball 0.5 mm pitch bga (top view) [3, 4, 5, 6, 7] CYDM064B16, cydm128b16, cydm256b16 1 2 3 4 5 6 7 8 9 10 a a 5r a 8r a 11r ub r v ss sem r io 15r io 12r io 10r v ss a b a 3r a 4r a 7r a 9r ce r r/w r oe r v ddior io 9r io 6r b c a 0r a 1r a 2r a 6r lb r irr1 [6] io 14r io 11r io 7r v ss c d odr4 odr2 busy r int r a 10r a 12r [3] io 13r io 8r io 5r io 2r d e v ss m/s odr3 int l v ss v ss io 4r v ddior io 1r v ss e f sfen odr1 busy l a 1l v cc v ss io 3r io 0r io 15l v ddiol f g odr0 a 2l a 5l a 12l [3] oe l io 3l io 11l io 12l io 14l io 13l g h a 0l a 4l a 9l lb l ce l io 1l v ddiol nc [7] nc [7] io 10l h j a 3l a 7l a 10l irr0 [5] v cc v ss io 4l io 6l io 8l io 9l j k a 6l a 8l a 11l ub l sem l r/w l io 0l io 2l io 5l io 7l k 1 2 3 4 5 6 7 8 9 10 notes 3. a12l and a12r are nc pins for CYDM064B16. 4. irr functionality is not supported for the cydm256b16 device. 5. this pin is a13l for cydm256b16 device. 6. this pin is a13r for cydm256b16 device. 7. leave this pin unconnected. no trace or pow er component can be connected to this pin. [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 5 of 27 table 1. pin definitions - 100-ball 0.5 mm pitch bga (CYDM064B16, cydm128b16, cydm256b16) left port right port description ce l ce r chip enable r/w l r/w r read or write enable oe l oe r output enable a 0l ?a 13l a 0r ?a 13r address (a 0 ?a 11 for 4k devices; a 0 ?a 12 for 8k devices; a 0 ?a 13 for 16k devices) io 0l ?io 15l io 0r ?io 15r data bus input or output for x16 devices sem l sem r semaphore enable ub l ub r upper byte select (io 8 ?io 15 ) lb l lb r lower byte select (io 0 ?io 7 ) int l int r interrupt flag busy l busy r busy flag irr0, irr1 input read register for CYDM064B16 and cydm128b16 a13l and a13r for cydm256b16. odr0-odr4 output drive register. these outputs are open drain. sfen special function enable m/s master or slave select v cc core power gnd ground v ddiol left port i/o voltage v ddior right port i/o voltage nc no connect. leave this pin unconnected. [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 6 of 27 functional description the cydm256b16, cydm128b16, and CYDM064B16 are low power cmos 4k, 8k,16k x 16 dual-port static rams. arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. two ports are provided that permit independent, asynchronous access for reads and writes to any location in memory. the devices can be used as standalone 16-bit dual-port static rams or multiple devices can be combined to function as a 32-bit or wider master/slave dual-port static ram. an m/s pin is provided for implementing 32-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. application areas include interproce ssor or multi- processor designs, communications status buffering, and dual-port video or graphics memory. each port has independent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy indicates that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) permits communication between ports or systems through a mail box. the semaphores are used to pass a flag or token, from one port to the other, to indicate that a shared resource is in use. the semaphore logic consists of eight shared latches. only one side can control the latch (semaphore) at any time. control of a semaphore indicates that a shared resource is in use. an automatic power down feature is controlled independently on each port by a chip enable (ce ) pin. the cydm256b16, cydm128b16, CYDM064B16 are available in 100-ball 0.5 mm pitch ball grid array (bga) packages. power supply the core voltage (v cc ) can be 1.8v, 2.5v, or 3.0v, as long as it is lower than or equal to the i/o voltage. each port can operate on independent i/o voltages. this is determined by what is connected to the v ddiol and v ddior pins. the supported i/o standards are 1.8v or 2.5v lvcmos and 3.0v lvttl. write operation data must be set up for a duration of t sd before the rising edge of r/w to guarantee a valid write. a write operation is controlled by either the r/w pin (see figure 5 on page 19) or the ce pin (see figure 6 on page 19). required inputs for noncontention operations are summarized in table 2 on page 8. if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output. otherwise, the data read is not deterministic. data is valid on the port t ddd after the data is presen ted on the other port. read operation when reading the device, the us er must assert both the oe and ce pins. data is available t ace after ce or t doe after oe is asserted. if the user wishes to access a semaphore flag, then the sem pin must be asserted instead of the ce pin, and oe must also be asserted. interrupts the upper two memory locations may be used for message passing. the highest memory location (fff for the CYDM064B16, 1fff for the cydm128b16, 3fff for the cydm256b16) is the mailbox for the right port and the second-highest memory location (ffe for the cydm 064b16, 1ffe for the cydm128b16, 3ffe for the cydm256b16) is the mailbox for the left port. when one port writes to the other port?s mailbox, an interrupt is generated to the owner. the interrupt is reset when the owner reads the contents of the mailbox. the message is user-defined. each port can read the other port?s mailbox without resetting the interrupt. the active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. if an application does not require message passing, do not connect the interrupt pin to the processor?s interrupt request input pin. on power up, an initialization program must be run and the interrupts for both ports must be read to reset them. the operation of the interrupts and their interaction with busy are summarized in table 3 on page 8 . busy the cydm256b16, cydm128b16, and CYDM064B16 provide on-chip arbitration to resolve simultaneous memory location access (contention). if both port ce s are asserted and an address match occurs within t ps of each other, the busy logic determines which port has access. if t ps is violated, one port definitely gains permission to the location. however, which port gets this permission cannot be predicted. busy is asserted t bla after an address match or t blc after ce is taken low. master/slave an m/s pin is provided to expand the word width by configuring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this allows the device to interface to a master device with no external components. writing to slave devices must be delayed until after the busy input has settled (t blc or t bla ). otherwise, the slave chip may begin a write cycle durin g a contention si tuation. when tied high, the m/s pin allows the device to be used as a master and, as a result, the busy line is an output. busy can then be used to send the arbitration outcome to a slave. [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 7 of 27 input read register the input read register (irr) captures the status of two external input devices that are connected to the input read pins. the contents of the irr read from address x0000 from either port. during reads from the irr, dq0 and dq1 are valid bits and dq<15:2> are don?t care. writes to address x0000 are not allowed from either port. address x0000 is not available for standard memory accesses when sfen = v il . when sfen = v ih , address x0000 is available for memory accesses. the inputs are 1.8v/2.5v lvcmos or 3.0v lvttl, depending on the core voltage supply (v cc ). refer to ta b l e 4 on page 9 for input read register operation. irr is not available in the cy dm256b16, because the irr pins are used as extra address pins a 13l and a 13r . output drive register the output drive register (odr) determines the state of up to five external binary state devices by providing a path to v ss for the external circuit. these outputs are open drain. the five external devices can operate at different voltages (1.5v v ddio 3.5v) but the combined current cannot exceed 40 ma (8 ma max for each external device). the status of the odr bits are set using standard write accesses from either port to address x0001 with a ?1? corresponding to on and ?0? corresponding to off. the status of the odr bits c an be read with a standard read access to address x0001. when sfen = v il , the odr is active and address x0001 is not available for memory accesses. when sfen = v ih , the odr is inactive and address x0001 can be used for standard accesses. during reads and writes to odr dq<4:0> are valid and dq<15:5> are don?t care. refer to ta b l e 5 on page 9 for output drive register operation. semaphore operation the cydm256b16, cydm128b16, and CYDM064B16 provide eight semaphore latches, which are separate from the dual-port memory locations. semaphores are used to reserve resources that are shared between the two ports. the state of the semaphore indicates that a resource is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before attempting to read the semaphore. the semaphore value is available t swrd + t doe after the rising edge of the semaphore write. if the left port is successful (reads a zero), it assumes control of the shared resource. otherwise (reads a one), it assumes the right port has control and continues to poll the semaphore. when the right side has relinquished control of the semaphore (by writing a one), the left side succeeds in gaining control of the semaphore. if the left side no longer requires the semaphore, a one is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip select for the semaphore latches (ce must remain high during sem low). a 0?2 represents the semaphore address. oe and r/w are used in the same manner as a normal memory access. when writing or reading a semaphore, the other addre ss pins have no effect. when writing to the semaphore, only io 0 is used. if a zero is written to the left port of an available semaphore, a one appears at the same semaphore address on the right port. that semaphore can now only be modified by the side showing zero (the left port in this case). if the left port now relinquishes control by writing a one to the semaphore, the semaphore is set to one for both sides. however, if the right port requests the semaphore (written a zero) while the left port has control, the right port immediately owns the semaphore as soon as the left port releases it. table 6 on page 9 shows sample semaphore operations. when reading a semaphore, all sixteen data lines output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore is definitely obtained by one side or the other, but there is no guarantee which side controls the semaphore. on power up, both ports must write ?1? to all eight semaphores. architecture the cydm256b16, cydm128b16, and CYDM064B16 consist of an array of 4k, 8k, or 16k words of 16 dual-port ram cells, i/o and address lines, and control signals (ce , oe , r/w ). these control pins permit independent access for reads or writes to any location in memory. to handle simultaneous writes or reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be used for port-to-port communication. two semaphore (sem ) control pins are used to allocate shared resources. with the m/s pin, the devices can function as a master (busy pins are outputs) or as a slave (busy pins are inputs). the devices also have an automatic power down feature controlled by ce . each port is provided with its own output enable control (oe ), which allows data to be read from the device. [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 8 of 27 table 2. noncontending read/write inputs outputs operation ce r/w oe ub lb sem io 8 ? io 15 io 0 ? io 7 h x x x x h high z high z deselected: power down x x x h h h high z high z deselected: power down l l x l h h data in high z write to upper byte only l l x h l h high z data in write to lower byte only l l x l l h data in data in write to both bytes l h l l h h data out high z read upper byte only l h l h l h high z data out read lower byte only l h l l l h data out data out read both bytes x x h x x x high z high z outputs disabled h h l x x l data out data out read data in semaphore flag x h l h h l data out data out read data in semaphore flag h x x x l data in data in write d in0 into semaphore flag x x h h l data in data in write d in0 into semaphore flag lxxlxl not allowed l x x x l l not allowed notes 8. see interrupts functional description for sp ecific highest memory locations by device. 9. if busy r = l, then no change. 10. if busy l = l, then no change. 11. see section functional description on page 6 for specific addresses by device. table 3. interrupt operation example (assumes busy l = busy r = high) [8] function left port right port r/w l ce l oe l a 0l?13l int l r/w r ce r oe r a 0r?13r int r set right int r flag llx 3fff [11] xx x x x l [10] reset right int r flag xxx x xxll 3fff [11] h [9] set left int l flag xxx x l [9] ll x 3ffe [11] x reset left int l flag xll 3ffe [11] h [10] xx x x x [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 9 of 27 table 4. input read register operation [12, 15] sfen ce r/w oe ub lb addr io 0 ? io 1 io 2 ? io 15 mode h l h l l l x0000-max valid [13] valid [13] standard memory access l l h l x l x0000 valid [14] x irr read table 5. output drive register [16] sfen ce r/w oe ub lb addr io 0 ? io 4 io 5 ? io 15 mode hlh x [17] l [13] l [13] x0000-max valid [13] valid [13] standard memory access l l l x x l x0001 valid [14] x odr write [16, 18] l l h l x l x0001 valid [14] x odr read [16] notes 12. sfen = v il for irr reads 13. ub or lb = v il . if lb = v il , then dq<7:0> are valid. if ub = v il then dq<15:8> are valid. 14. lb must be active (lb = v il ) for these bits to be valid. 15. sfen active when either ce l = v il or ce r = v il . it is inactive when ce l = ce r = v ih . 16. sfen = v il for odr reads and writes. 17. output enable must be low (oe = v il ) during reads for valid data to be output. 18. during odr writes data are also written to the memory. table 6. semaphore operation example function io 0 ? io 15 left io 0 ? io 15 right status no action 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token right port writes 0 to semaphore 0 1 no change. right side has no write access to semaphore. left port writes 1 to semaphore 1 0 right port obtains semaphore token left port writes 0 to semaphore 1 0 no change. left port has no write access to semaphore. right port writes 1 to semaphore 0 1 left port obtains semaphore token left port writes 1 to semaphore 1 1 semaphore free right port writes 0 to semaphore 1 0 right port has semaphore token right port writes 1 to semaphore 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token left port writes 1 to semaphore 1 1 semaphore free [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 10 of 27 maximum ratings exceeding maximum ratings [19] may shorten the useful life of the device. user guidelines are not tested. storage temperature ................ .............. ... ?65c to +150c ambient temperature with power applied ............ ............... .............. ... ?55c to +125c supply voltage to ground potentia l................?0.5v to +3.3v dc voltage applied to outputs in high z state ......................... ?0.5v to v cc + 0.5v dc input voltage [20] ............................... ?0.5v to v cc + 0.5v output current into outputs (low)............................. 90 ma static discharge voltage....... ........... ............ ............ > 2000v latch-up current ................................................... > 200 ma operating range range ambient temperature v cc commercial 0c to +70c 1.8v 100 mv 2.5v 100 mv 3.0v 300 mv industrial ?40c to +85c 1.8v 100 mv 2.5v 100 mv 3.0v 300 mv notes 19. the voltage on any input or i/o pin can not exceed the power pin during power up. 20. pulse width < 20 ns. electrical characteristics for v cc = 1.8v over the operating range parameter description cydm256b16, cydm128b16, CYDM064B16 unit -55 p1 i/o voltage p2 i/o voltage min typ. max v oh output high voltage (i oh = ?100 a) 1.8v (any port) v ddio ? 0.2 v output high voltage (i oh = ?2 ma) 2.5v (any port) 2.0 v output high voltage (i oh = ?2 ma) 3.0v (any port) 2.1 v v ol output low voltage (i ol = 100 a ) 1.8v (any port) 0.2 v output high voltage (i ol = 2 ma) 2.5v (any port) 0.4 v output high voltage (i ol = 2 ma) 3.0v (any port) 0.4 v v ol odr odr output low voltage (i ol = 8 ma ) 1.8v (any port) 0.2 v 2.5v (any port) 0.2 v 3.0v (any port) 0.2 v v ih input high voltage 1.8v (any port) 1.2 v ddio + 0.2 v 2.5v (any port) 1.7 v ddio + 0.3 v 3.0v (any port) 2.0 v ddio + 0.2 v v il input low voltage 1.8v (any port) ?0.2 0.4 v 2.5v (any port) ?0.3 0.6 v 3.0v (any port) ?0.2 0.7 v i oz output leakage current 1.8v 1.8v ?1 1 a 2.5v 2.5v ?1 1 a 3.0v 3.0v ?1 1 a i cex odr odr output leakage current. v out =v ddio 1.8v 1.8v ?1 1 a 2.5v 2.5v ?1 1 a 3.0v 3.0v ?1 1 a i ix input leakage current 1.8v 1.8v ?1 1 a 2.5v 2.5v ?1 1 a 3.0v 3.0v ?1 1 a [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 11 of 27 i cc operating current (v cc = max., i out = 0 ma) outputs disabled ind. 1.8v 1.8v 15 25 ma i sb1 standby current (both ports ttl level) ce l and ce r v cc ? 0.2, sem l = sem r = v cc ? 0.2, f = f max ind. 1.8v 1.8v 2 6 a i sb2 standby current (one port ttl level) ce l | ce r v ih , f = f max ind. 1.8v 1.8v 8.5 14 ma i sb3 standby current (both ports cmos level) ce l and ce r v cc ? 0.2v, sem l and sem r > v cc ? 0.2v, f = 0 ind. 1.8v 1.8v 2 6 a i sb4 standby current (one port cmos level) ce l | ce r v ih , f = f max [21] ind. 1.8v 1.8v 8.5 14 ma electrical characteristics for v cc = 1.8v (continued) over the operating range parameter description cydm256b16, cydm128b16, CYDM064B16 unit -55 p1 i/o voltage p2 i/o voltage min typ. max notes 21. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 . electrical characteristics for v cc = 2.5v over the operating range parameter description cydm256b16, cydm128b16, CYDM064B16 unit -55 p1 i/o voltage p2 i/o voltage min typ. max v oh output high voltage (i oh = ?2 ma) 2.5v (any port) 2.0 v 3.0v (any port) 2.1 v v ol output low voltage (i ol = 2 ma ) 2.5v (any port) 0.4 v 3.0v (any port) 0.4 v v ol odr odr output low voltage (i ol = 8 ma ) 2.5v (any port) 0.2 v 3.0v (any port) 0.2 v v ih input high voltage 2.5v (any port) 1.7 v ddio + 0.3 v 3.0v (any port) 2.0 v ddio + 0.2 v v il input low voltage 2.5v (any port) ?0.3 0.6 v 3.0v (any port) ?0.2 0.7 v i oz output leakage current 2.5v 2.5v ?1 1 a 3.0v 3.0v ?1 1 a i cex odr odr output leakage current. v out =v cc 2.5v 2.5v ?1 1 a 3.0v 3.0v ?1 1 a i ix input leakage current 2.5v 2.5v ?1 1 a 3.0v 3.0v ?1 1 a i cc operating current (v cc = max., i out = 0 ma) outputs disabled ind. 2.5v 2.5v 28 40 ma [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 12 of 27 i sb1 standby current (both ports ttl level) ce l and ce r v cc ? 0.2, sem l = sem r = v cc ? 0.2, f = f max ind. 2.5v 2.5v 6 8 a i sb2 standby current (one port ttl level) ce l | ce r v ih , f = f max ind. 2.5v 2.5v 18 25 ma i sb3 standby current (both ports cmos level) ce l and ce r v cc ? 0.2v, sem l and sem r > v cc ? 0.2v, f = 0 ind. 2.5v 2.5v 4 6 a i sb4 standby current (one port cmos level) ce l | ce r v ih , f = f max [21] ind. 2.5v 2.5v 18 25 ma electrical characteristics for v cc = 2.5v (continued) over the operating range parameter description cydm256b16, cydm128b16, CYDM064B16 unit -55 p1 i/o voltage p2 i/o voltage min typ. max electrical characteristics for 3.0v over the operating range parameter description cydm256b16, cydm128b16, CYDM064B16 unit -55 p1 i/o voltage p2 i/o voltage min typ. max v oh output high voltage (i oh = ?2 ma) 3.0v (any port) 2.1 v v ol output low voltage (i ol = 2 ma ) 3.0v (any port) 0.4 v v ol odr odr output low voltage (i ol = 8 ma ) 3.0v (any port) 0.2 v v ih input high voltage 3.0v (any port) 2.0 v ddio + 0.2 v v il input low voltage 3.0v (any port) ?0.2 0.7 v i oz output leakage current 3.0v 3.0v ?1 1 a i cex odr odr output leakage current. v out =v cc 3.0v 3.0v ?1 1 a i ix input leakage current 3.0v 3.0v ?1 1 a i cc operating current (v cc = max., i out = 0 ma) outputs disabled ind. 3.0v 3.0v 42 60 ma i sb1 standby current (both ports ttl level) ce l and ce r v cc ? 0.2, sem l = sem r = v cc ? 0.2, f = f max ind. 3.0v 3.0v 7 10 a i sb2 standby current (one port ttl level) ce l | ce r v ih , f = f max ind. 3.0v 3.0v 25 35 ma i sb3 standby current (both ports cmos level) ce l and ce r v cc ? 0.2v, sem l and sem r > v cc ? 0.2v, f = 0 ind. 3.0v 3.0v 6 8 a i sb4 standby current (one port cmos level) ce l | ce r v ih , f = f max [21] ind. 3.0v 3.0v 25 35 ma note 22. tested initially and after any design or proce ss changes that may affect these parameters. capacitance [22] parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = 3.0v 9pf c out output capacitance 10 pf [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 13 of 27 ac test loads and waveforms 1.8v gnd 90% 90% 10% 10% all input pulses (a) normal load r1 3.0v/2.5v/1.8v output r2 c = 30 pf v th = 0.8v output (b) thvenin equivalent (load 1) (c) three-state delay (load 2) r1 r2 3.0v/2.5v/1.8v output r th = 6 k 3 ns 3 ns including scope and jig) (used for t lz , t hz , t hzwe , and t lzwe 3.0v/2.5v 1.8v r1 1022 13500 r2 792 10800 c = 30 pf c = 5 pf notes 23. test conditions assume signal transition time of 3 ns or less, timing reference levels of v cc /2, input pulse levels of 0 to v cc , and output loading of the specified i oi /i oh and 30 pf load capacitance. 24. to access ram, ce = l, ub = l, sem = h. to access semaphore, ce = h and sem = l. either condition must be valid for the entire t sce time. 25. at any temperature and voltage condition for any device, t hzce is less than t lzce and t hzoe is less than t lzoe . 26. test conditions used are load 3. 27. this parameter is guaranteed but not tested. for information on port-to-port delay through ram cells from writing port to re ading port, refer to read timing with busy waveform. switching characteristics for v cc = 1.8v over the operating range [23] parameter description cydm256b16, cydm128b16, CYDM064B16 unit -55 min max read cycle t rc read cycle time 55 ns t aa address to data valid 55 ns t oha output hold from address change 5 ns t ace [24] ce low to data valid 55 ns t doe oe low to data valid 30 ns t lzoe [25, 26, 27] oe low to low z 5 ns t hzoe [25, 26, 27] oe high to high z 25 ns t lzce [25, 26, 27] ce low to low z 5 ns t hzce [25, 26, 27] ce high to high z 25 ns t pu [27] ce low to power up 0 ns t pd [27] ce high to power down 55 ns t abe [24] byte enable access time 55 ns [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 14 of 27 write cycle t wc write cycle time 55 ns t sce [24] ce low to write end 45 ns t aw address valid to write end 45 ns t ha address hold from write end 0 ns t sa [24] address setup to write start 0 ns t pwe write pulse width 40 ns t sd data setup to write end 30 ns t hd data hold from write end 0 ns t hzwe [26, 27] r/w low to high z 25 ns t lzwe [26, 27] r/w high to low z 0 ns t wdd [28] write pulse to data delay 80 ns t ddd [28] write data valid to read data valid 80 ns busy timing [29] t bla busy low from address match 45 ns t bha busy high from address mismatch 45 ns t blc busy low from ce low 45 ns t bhc busy high from ce high 45 ns t ps [30] port setup for priority 5 ns t wb r/w high after busy (slave) 0 ns t wh r/w high after busy high (slave) 35 ns t bdd [31] busy high to data valid 40 ns interrupt timing [29] t ins int set time 45 ns t inr int reset time 45 ns semaphore timing t sop sem flag update pulse (oe or sem )15 ns t swrd sem flag write to read time 10 ns t sps sem flag contention window 10 ns t saa sem address access time 55 ns switching characteristics for v cc = 1.8v (continued) over the operating range [23] parameter description cydm256b16, cydm128b16, CYDM064B16 unit -55 min max notes 28. for information on port-to-port delay through ram cells from writing port to reading port, refer to read timing with busy wa veform. 29. test conditions used are load 2. 30. add 2ns to this parameter if v cc and v ddior are <1.8v, and v ddiol is >2.5v at temperature <0c. 31. t bdd is a calculated parameter and is the greater of t wdd ? t pwe (actual) or t ddd ? t sd (actual). [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 15 of 27 switching characteristics for v cc = 2.5v over the operating range parameter description cydm256b16, cydm128b16, CYDM064B16 unit -55 min max read cycle t rc read cycle time 55 ns t aa address to data valid 55 ns t oha output hold from address change 5 ns t ace [24] ce low to data valid 55 ns t doe oe low to data valid 30 ns t lzoe [25, 26, 27] oe low to low z 2 ns t hzoe [25, 26, 27] oe high to high z 25 ns t lzce [25, 26, 27] ce low to low z 2 ns t hzce [25, 26, 27] ce high to high z 25 ns t pu [27] ce low to power up 0 ns t pd [27] ce high to power down 55 ns t abe [24] byte enable access time 55 ns write cycle t wc write cycle time 55 ns t sce [24] ce low to write end 45 ns t aw address valid to write end 45 ns t ha address hold from write end 0 ns t sa [24] address setup to write start 0 ns t pwe write pulse width 40 ns t sd data setup to write end 30 ns t hd data hold from write end 0 ns t hzwe [26, 27] r/w low to high z 25 ns t lzwe [26, 27] r/w high to low z 0 ns t wdd [28] write pulse to data delay 80 ns t ddd [28] write data valid to read data valid 80 ns busy timing [29] t bla busy low from address match 45 ns t bha busy high from address mismatch 45 ns t blc busy low from ce low 45 ns t bhc busy high from ce high 45 ns t ps [30] port setup for priority 5 ns t wb r/w high after busy (slave) 0 ns t wh r/w high after busy high (slave) 35 ns t bdd [31] busy high to data valid 40 ns [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 16 of 27 interrupt timing [29] t ins int set time 45 ns t inr int reset time 45 ns semaphore timing t sop sem flag update pulse (oe or sem )15 ns t swrd sem flag write to read time 10 ns t sps sem flag contention window 10 ns t saa sem address access time 55 ns switching characteristics for v cc = 3.0v over the operating range parameter description cydm256b16, cydm128b16, CYDM064B16 unit -55 min max read cycle t rc read cycle time 55 ns t aa address to data valid 55 ns t oha output hold from address change 5 ns t ace [24] ce low to data valid 55 ns t doe oe low to data valid 30 ns t lzoe [25, 26, 27] oe low to low z 1 ns t hzoe [25, 26, 27] oe high to high z 25 ns t lzce [25, 26, 27] ce low to low z 1 ns t hzce [25, 26, 27] ce high to high z 25 ns t pu [27] ce low to power up 0 ns t pd [27] ce high to power down 55 ns t abe [24] byte enable access time 55 ns write cycle t wc write cycle time 55 ns t sce [24] ce low to write end 45 ns t aw address valid to write end 45 ns t ha address hold from write end 0 ns t sa [24] address setup to write start 0 ns t pwe write pulse width 40 ns t sd data setup to write end 30 ns t hd data hold from write end 0 ns switching characteristics for v cc = 2.5v (continued) over the operating range parameter description cydm256b16, cydm128b16, CYDM064B16 unit -55 min max [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 17 of 27 t hzwe [26, 27] r/w low to high z 25 ns t lzwe [26, 27] r/w high to low z 0 ns t wdd [28] write pulse to data delay 80 ns t ddd [28] write data valid to read data valid 80 ns busy timing [29] t bla busy low from address match 45 ns t bha busy high from address mismatch 45 ns t blc busy low from ce low 45 ns t bhc busy high from ce high 45 ns t ps [30] port setup for priority 5 ns t wb r/w high after busy (slave) 0 ns t wh r/w high after busy high (slave) 35 ns t bdd [31] busy high to data valid 40 ns interrupt timing [29] t ins int set time 45 ns t inr int reset time 45 ns semaphore timing t sop sem flag update pulse (oe or sem )15 ns t swrd sem flag write to read time 10 ns t sps sem flag contention window 10 ns t saa sem address access time 55 ns switching characteristics for v cc = 3.0v (continued) over the operating range parameter description cydm256b16, cydm128b16, CYDM064B16 unit -55 min max notes 32. r/w is high for read cycles. 33. device is continuously selected ce = v il and ub or lb = v il . this waveform cannot be used for semaphore reads. 34. oe = v il . 35. address valid before or coincident with ce transition low. 36. to access ram, ce = v il , ub or lb = v il , sem = v ih . to access semaphore, ce = v ih , sem = v il . 37. r/w must be high during all address transitions. 38. a write occurs during the overlap (t sce or t pwe ) of a low ce or sem and a low ub or lb . [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 18 of 27 switching waveforms figure 2. read cycle no.1 (either port address access) [32, 33, 34] figure 3. read cycle no.2 (either port ce /oe access) [32, 35, 36] figure 4. read cycle no. 3 (either port) [32, 34, 37, 38] t rc t aa t oha data valid previous data valid data out address t oha t ace t lzoe t doe t hzoe t hzce data valid t lzce t pu t pd i sb i cc data out oe ce and lb or ub current ub or lb data out t rc address t aa t oha ce t lzce t abe t hzce t hzce t ace t lzce [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 19 of 27 figure 5. write cycle no.1: r/w controlled timing [37, 38, 39, 40, 41, 42] figure 6. write cycle no. 2: ce controlled timing [37, 38, 39, 44] switching waveforms (continued) t aw t wc t pwe t hd t sd t ha ce r/w oe data out data in address t hzoe t sa t hzwe t lzwe [43] [43] [40] [41, 42] note 44 note 44 t aw t wc t sce t hd t sd t ha ce r/w data in address t sa [41, 42] notes 39. t ha is measured from the earlier of ce or r/w or (sem or r/w ) going high at the end of write cycle. 40. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during an r/w controlled write cycle, this requirement does not ap ply and the write pulse can be as short as the specified t pwe . 41. to access ram, ce = v il , sem = v ih . 42. to access upper byte, ce = v il , ub = v il , sem = v ih . to access lower byte, ce = v il , lb = v il , sem = v ih . 43. transition is measured 0 mv from steady state with a 5 pf load (including scope and jig). this parameter is sampled and not 100% tested. 44. during this period, the i/o pins are in the output state, and input signals must not be applied. [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 20 of 27 figure 7. semaphore read after write timing (either side) [45, 46] figure 8. timing diagram of semaphore contention [47, 48] notes 45. if the ce or sem low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high impedance state. 46. ce = high for the duration of the above timing (both write and read cycle). 47. io 0r = io 0l = low (request semaphore); ce r = ce l = high. 48. if t sps is violated, the semaphore is definitely obtained by one side or the other, but the side that gets the semaphore cannot be pre dicted. switching waveforms (continued) t sop t saa valid adress valid adress t hd data in valid t oha t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle oe r/w io 0 sem a 0 ?a 2 data out valid match t sps match r/w l sem l r/w r sem r a 0l ?a 2l a 0r ?a 2r [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 21 of 27 figure 9. timing di agram of read with busy (m/s = high) [49] figure 10. write timing with busy input (m/s = low) note 49. ce l = ce r = low. switching waveforms (continued) valid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe valid t sd t hd address l t ps t bla t bha t bdd busy l t pwe r/w busy t wb t wh [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 22 of 27 figure 11. busy timing diagram no.1 (ce arbitration) figure 12. busy timing diagram no.2 (address arbitration) [50] note 50. if t ps is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side busy i s asserted. switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc ce r valid first address l,r busy r ce l ce r busy l ce r ce l address l,r ce l valid first [50] address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first left address valid first 1. [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 23 of 27 figure 13. interrupt timing diagrams switching waveforms (continued) write 1fff (or 1/3fff) t wc right side clears int r t ha read 1fff t rc t inr write 1ffe (or 1/3ffe) t wc right side sets int l left side sets int r left side clears int l read 1ffe t inr t rc address l ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r address l r/w l ce l int r t ins t ha t ins (or 1/3fff) or 1/3ffe) [51] [52] [52] [52] [51] [52] notes 51. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 52. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 24 of 27 ordering information ordering code defintions table 7. 16k x 16 1.8v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 55 cydm256b16-55bvxc bz100 100-ball pb-free 0.5 mm pitch bga commercial 55 cydm256b16-55bvxi bz100 100-ball pb-free 0.5 mm pitch bga industrial table 8. 8k x16 1.8v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 55 cydm128b16-55bvxc bz100 100-ball pb-free 0.5 mm pitch bga commercial 55 cydm128b16-55bvxi bz100 100-ball pb-free 0.5 mm pitch bga industrial table 9. 4k x16 1.8v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 55 CYDM064B16-55bvxc bz100 100-ball pb-free 0.5 mm pitch bga commercial 55 CYDM064B16-55bvxi bz100 100-ball pb-free 0.5 mm pitch bga industrial [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 25 of 27 package diagram figure 14. 100 vfbga (6 6 1.0 mm) bz100a 51-85209 *d [+] feedback
CYDM064B16 cydm128b16 cydm256b16 document #: 001-00217 rev. *h page 26 of 27 document history page document title: CYDM064B16, cydm128b16, cydm256b16 1.8v 4k/8k/16k x 16 mobl ? dual-port static ram document number: 001-00217 revision ecn orig. of change submission date description of change ** 369423 ydt 05/23/05 new datasheet *a 381721 ydt see ecn updated 2.5v/3.0v icc, isb1, isb2, isb4 updated vol odr to 0.2v *b 396697 kgh see ecn updated isb2 and isb4 typo to ma. updated tins and tinr for -55 to 31 ns. *c 404777 kgh see ecn updated i oh and i ol values for the 1.8v, 2.5v and 3.0v parameters v oh and v ol replaced -35 speed bin with -40 updated switching characteristics for v cc = 2.5v and v cc = 3.0v included note 35 *d 426637 kgh see ecn removed part numbers cydm128b08 and cydm064b08 *e 733676 hkh see ecn corrected typo for power supply description in page 4 (3.0v instead of 3.3v) updated tddd timing value to be consistent with twdd *f 2545957 ogc/aesa 07/31/2008 removed all details of -40 ns parts. updated datasheet template. *g 2920132 ogc 04/26/10 removed reference to x8 part in title. document title changed to ?CYDM064B16, cydm128b16, cydm256b16 1.8v 4k/8k/16k x 16 mobl ? dual-port static ram? *h 3183900 esh 02/28/11 added ordering code definitions. [+] feedback
document #: 001-00217 rev. *h revised march 1, 2011 page 27 of 27 all products and company names mentioned in this document may be the trademarks of their respective holders. CYDM064B16 cydm128b16 cydm256b16 ? cypress semiconductor corporation, 2005-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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